Vision and Background: MSDLab @ IISc Bangalore (India) & ESD Association (USA) have envisioned a need to strengthen and promote ESD design activities in India through a forum what now call “India ESD Forum”. IEW is an outcome of this forum with following four fold vision. First, to increase ESD awareness among engineers and academicians working in the field of VLSI / Microelectronics and would like to learn or engage into ESD protection device/circuit/product design and testing activities. Second, to bring engineers together who encounter ESD problems in their designs. Third, to promote research, development and training related to on-chip ESD device/circuit design in India. Finally, the most important, to use this model to strengthen academia-Industry partnership in and around country.
Predominant failure mechanism: It is estimated that above ~25% of component failures are due to Electrical Overstress (EOS) and Electrostatic Discharge (ESD).
Changing Technologies: Constantly changing technologies make the ESD protection design challenging. Learning from past Si technologies is no more sufficient.
Reliable Chips: For reliable operation of Integrated circuits ESD continues to be a major concern.